Verilog for an FPGA Engineer with Xilinx Vivado Design Suite

Verilog for an FPGA Engineer with Xilinx Vivado Design Suite

Using Xilinx FPGA's

英语 [自动]

https://www.udemy.com/course/verilog-for-an-engineer-with-xilinx-vivado-design-suite/

24 个章节 • 168 个讲座 • 总时长 17 小时 45 分钟

你将会学到的



Fundamentals of Verilog Programming that will help to ace RTL Engineer Job Interviews.



Understand Vivado Design Suite flow for Digital System Design.



Hardware Debugging in Vivado viz. Integrated Logic Analyzer, Virtual I/O.



Different Modelling Styles in Hardware Description Language.



How to use Xilinx IP's and create Custom IP's.



IP integrator Design flow of the Vivado.



Writing Verilog Test benches.



Design of some real world projects such as : PMOD DA4 DAC interface, Function Generator, Small Processor Architecture, UART Interface, PWM, BIST for Development boards and many more.



Common Interview Questions



要求



Fundamental of Digital Circuit will give an added advantages.



说明



This Course will teach you Fundamentals of Verilog which every VLSI Job aspirant must know before appearing for the Recruitment process or anyone interested in FPGA's. The course will explore various Verilog constructs through real system examples along with assignments, quizzes to enhance learning. Each module consists of some discussion on common interview questions to create a framework for Interview preparation. The entire course is taught using the Xilinx Vivado Design Suite to give practical exposure with Industry's most popular Toolsets.







此课程面向哪些人：



VLSI Job Seeker/ Graduate student looking to pursue career as RTL Engineer/ Design Engineer/ Verification Engineer.



Anyone interested to learn Xilinx FPGA/ Vivado Design Suite/ Verilog Hardware Description Language



Anyone interested to start career in ASIC/ VLSI domain.