Video Processing with FPGA

Video Processing with FPGA

https://www.udemy.com/course/video-processing-with-fpga/

Implementing different Computer Vision Algorithm on Xilinx Zynq FPGA with VIVADO High Level Synthesis & SDK

上次更新 7/2020

英语 [自动]

你将会学到的

Implement different Computer Vision algorithm for Video Processing

Creating IP from the VIVADO High Level Synthesis

IP integration and configuration with Xilinx VIVADO

Xilinx SDK Application Development

Migrating the OpenCV algorithm on XfOpenCV

Simulating & Generating XfOpenCV codes in the VIVADO HLS

Integrating TPG, VDMA and Writing application for this blocks

要求

Basics of FPGA Design

High Level Synthesis Basics

PC with installed VIVADO, HLS and SDK [we will also show the steps for installation]

说明

This Course is on implementing different Video Processing algorithm on FPGA. We implement the algorithm on High Level Synthesis [HLS], simulate it with the image input, generate & export IP from the HLS. The HLS IP is integrated with the necessary video processing pipeline [block design] and implemented on the FPGA Device.



We have "Implemented Sobel Edge Detection, Dilation, Histogram Equalize, Fast Corner like algorithm" on HLS and then FPGA. For the debugging the algorithm on the FPGA, we have initialized the Test Pattern Generator [TPG] IP and Video DMA [VDMA] for processing the image streams on the DDR with the Processing System involvement.



After Completing this course you will be able to:



Utilized the HLS Video Processing Library and Implement as well as Simulate different OpenCV Algorithm on HLS



Integrating the HLS IP with Video Processing Pipeline with TPG and VDMA and Implementing on the FPGA Device.



Implementing the XfOpenCV [SDSoC] Library on HLS for Computer Vision



Migrating the OpenCV algorithm into XfOpenCV



此课程面向哪些人：

Electrical Engineering Enthusiast

Computer Science Enthusiast

FPGA Design Professional

Enthusiast of FPGA Design